module test_top(
    input  wire clk,             // System clock 50 MHz
    input  wire rst_n,           // Active-low reset
    input  wire LR,              // Left/Right channel select
    

    output wire [7:0] digit_seg,
    output wire [3:0] digit_dig
 );
    wire [23:0] number;
    assign number=24'hAFCE66;
    
    
    wire [15:0] b16_data;
    wire        b16_data_vld;

    from_24bit_to_16bit u_24_to_16 (
        .rst_n        (rst_n),
        .clk          (clk),
        .data_vld_in  (1'b1),
        .data_in      (number),
        .data_vld_out (b16_data_vld),
        .data_out     (b16_data)
    );
    

    // ===============================
    // 数码管显示（HEX）
    // ===============================
    wire [3:0] dig3 = b16_data[15:12];
    wire [3:0] dig2 = b16_data[11:8];
    wire [3:0] dig1 = b16_data[7:4];
    wire [3:0] dig0 = b16_data[3:0];

    digitshow u_digit (
        .clk       (clk),
        .rst_n     (rst_n),
        .data_in_1 (dig0),
        .data_in_2 (dig1),
        .data_in_3 (dig2),
        .data_in_4 (dig3),
        .data_vld  (4'b1111),
        .seg       (digit_seg),
        .dig       (digit_dig)
    );



endmodule
